This invention relates to programmable logic devices (“PLDs”), and more particularly to more economical clustering of logic modules and related circuitry in PLDs.
A PLD may include a large number of relatively small modules of programmable logic. For example, each such logic module (“LM”) or logic element (“LE”) may include a four-input look-up table (“LUT”), a register (e.g., for selectively registering an output signal of the LUT), and a small amount of other circuitry (e.g., for determining whether and how the register is used, for selecting control signals for the register, etc.). The LUT may be programmable to produce an output signal that is any logical combination or function of the four inputs to the LUT. The LE may be programmable with respect to whether and how the register is used, and what control signals (e.g., clock, clock enable, clear, etc.) are selected for application to the register.
In addition to the LEs, a PLD typically includes programmable interconnection circuitry for conveying signals to, from, and/or between the LEs in any of many different ways. This allows the relatively simple logic capabilities of individual LEs to be concatenated to perform logic tasks of considerable complexity.
It has been found helpful and economical to give the resources in PLDs—especially large PLDs—a hierarchical organization. For example, the LEs in a PLD may be clustered in groups that may be called logic array blocks or LABs. The LEs in a LAB share certain resources associated with the LAB. These shared resources may include such things as LAB input multiplexers (“LIMs”), which are programmable to select signals from nearby interconnection conductors so that those signals will be available as inputs to the LEs in the LAB. Another example of a resource that may be shared by the LEs in a LAB is so-called secondary signal (“SS”) selection circuitry. This SS circuitry is programmable to select signals from nearby conductors so that these signals will be available as secondary signals (e.g., register clock, clock enable, and clear signals) for use by the LEs in the LAB.
The manner in which a hierarchical PLD organization is implemented and the manner in which resources are shared by clusters of LEs in such a hierarchy can have a significant impact on the efficiency with which the “real estate” of the PLD is utilized. Improvements are therefore always being sought in this aspect of PLD design.